gn analyze output: { "compile_targets": [], "status": "Found dependency", "test_targets": [ "//clang-tools-extra/clangd/test:check-clangd", "//clang-tools-extra/test:check-clang-tools", "//clang/test:check-clang", "//compiler-rt/test/hwasan:check-hwasan", "//lld/test:check-lld", "//llvm/test:check-llvm" ] } gn analyze input: { "files": [ "//llvm/docs/MIRLangRef.rst", "//llvm/include/llvm/CodeGen/MachineInstr.h", "//llvm/include/llvm/Support/TargetOpcodes.def", "//llvm/include/llvm/Target/Target.td", "//llvm/lib/CodeGen/ExpandPostRAPseudos.cpp", "//llvm/lib/CodeGen/MachineFunction.cpp", "//llvm/lib/CodeGen/PeepholeOptimizer.cpp", "//llvm/lib/CodeGen/RegisterCoalescer.cpp", "//llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp", "//llvm/lib/CodeGen/TargetRegisterInfo.cpp", "//llvm/lib/CodeGen/TwoAddressInstructionPass.cpp", "//llvm/lib/Target/AArch64/AArch64FastISel.cpp", "//llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp", "//llvm/lib/Target/AArch64/AArch64ISelLowering.cpp", "//llvm/lib/Target/AArch64/AArch64InstrAtomics.td", "//llvm/lib/Target/AArch64/AArch64InstrFormats.td", "//llvm/lib/Target/AArch64/AArch64InstrInfo.cpp", "//llvm/lib/Target/AArch64/AArch64InstrInfo.td", "//llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp", "//llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td", "//llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp", "//llvm/lib/Target/AArch64/SVEInstrFormats.td", "//llvm/lib/Target/ARM/ARMInstrNEON.td", "//llvm/lib/Target/BPF/BPFInstrInfo.td", "//llvm/lib/Target/BPF/BPFMIPeephole.cpp", "//llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp", "//llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp", "//llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td", "//llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td", "//llvm/lib/Target/MSP430/MSP430InstrInfo.td", "//llvm/lib/Target/Mips/Mips64r6InstrInfo.td", "//llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp", "//llvm/lib/Target/Mips/MipsSEISelLowering.cpp", "//llvm/lib/Target/PowerPC/PPCISelLowering.cpp", "//llvm/lib/Target/PowerPC/PPCInstrP10.td", "//llvm/lib/Target/PowerPC/PPCInstrVSX.td", "//llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp", "//llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp", "//llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp", "//llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h", "//llvm/lib/Target/RISCV/RISCVFeatures.td", "//llvm/lib/Target/RISCV/RISCVSubtarget.cpp", "//llvm/lib/Target/RISCV/RISCVSubtarget.h", "//llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp", "//llvm/lib/Target/X86/X86FastISel.cpp", "//llvm/lib/Target/X86/X86ISelDAGToDAG.cpp", "//llvm/lib/Target/X86/X86ISelLowering.cpp", "//llvm/lib/Target/X86/X86InstrAVX512.td", "//llvm/lib/Target/X86/X86InstrCompiler.td", "//llvm/lib/Target/X86/X86InstrExtension.td", "//llvm/lib/Target/X86/X86InstrInfo.cpp", "//llvm/lib/Target/X86/X86InstrMisc.td", "//llvm/lib/Target/X86/X86InstrSSE.td", "//llvm/lib/Target/X86/X86InstrSystem.td", "//llvm/lib/Target/X86/X86InstrVecCompiler.td", "//llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp", "//llvm/test/CodeGen/AArch64/GlobalISel/166563.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir", "//llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir", "//llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir", "//llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir", "//llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir", "//llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir", "//llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir", "//llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir", "//llvm/test/CodeGen/AArch64/addsub.ll", "//llvm/test/CodeGen/AArch64/bf16_fast_math.ll", "//llvm/test/CodeGen/AArch64/coalescer-drop-subreg-to-reg-imm-ops.mir", "//llvm/test/CodeGen/AArch64/instr-ref-ldv.ll", "//llvm/test/CodeGen/AArch64/loop-sink.mir", "//llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir", "//llvm/test/CodeGen/AArch64/peephole-movd.mir", "//llvm/test/CodeGen/AArch64/peephole-sxtw.mir", "//llvm/test/CodeGen/AArch64/ptrauth-isel.ll", "//llvm/test/CodeGen/AArch64/ptrauth-isel.mir", "//llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir", "//llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir", "//llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir", "//llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir", "//llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir", "//llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir", "//llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir", "//llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir", "//llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir", "//llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir", "//llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir", "//llvm/test/CodeGen/AArch64/sms-regpress.mir", "//llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir", "//llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir", "//llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir", "//llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir", "//llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir", "//llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir", "//llvm/test/CodeGen/PowerPC/mi-simplify-code.mir", "//llvm/test/CodeGen/PowerPC/subreg-coalescer.mir", "//llvm/test/CodeGen/PowerPC/xxinsertw.ll", "//llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir", "//llvm/test/CodeGen/X86/GlobalISel/select-ext.mir", "//llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir", "//llvm/test/CodeGen/X86/apx/foldimmediate.mir", "//llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir", "//llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll", "//llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir", "//llvm/test/CodeGen/X86/coalescer-implicit-def-regression.mir", "//llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir", "//llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir", "//llvm/test/CodeGen/X86/foldimmediate.mir", "//llvm/test/CodeGen/X86/opt_phis2.mir", "//llvm/test/CodeGen/X86/peephole-test-after-add.mir", "//llvm/test/CodeGen/X86/peephole.mir", "//llvm/test/CodeGen/X86/pr57673.ll", "//llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir", "//llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir", "//llvm/test/CodeGen/X86/statepoint-invoke-ra.mir", "//llvm/test/CodeGen/X86/statepoint-vreg-details.ll", "//llvm/test/CodeGen/X86/subreg-fail.mir", "//llvm/test/CodeGen/X86/tail-dup-asm-goto.ll", "//llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir", "//llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir", "//llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir", "//llvm/test/DebugInfo/MIR/X86/machine-cse.mir", "//llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll", "//llvm/test/TableGen/GlobalISelEmitter/Subreg.td", "//llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected", "//llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected", "//llvm/utils/TableGen/GlobalISelEmitter.cpp", "//mlir/include/mlir/Dialect/MPI/IR/MPIOps.td", "//mlir/include/mlir/Dialect/MPI/IR/Utils.h", "//mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp", "//mlir/lib/Conversion/ShardToMPI/ShardToMPI.cpp", "//mlir/lib/Dialect/MPI/IR/MPIOps.cpp", "//mlir/test/Conversion/MPIToLLVM/mpitollvm.mlir", "//mlir/test/Conversion/ShardToMPI/convert-shard-to-mpi.mlir", "//mlir/test/Dialect/MPI/canonicalize.mlir", "//mlir/test/Dialect/Shard/partition.mlir" ], "test_targets": [ "//clang-tools-extra/clangd/test:check-clangd", "//clang-tools-extra/test:check-clang-tools", "//clang/test:check-clang", "//compiler-rt/test/hwasan:check-hwasan", "//lld/test:check-lld", "//llvm/test:check-llvm" ], "additional_compile_targets": [] } running all tests due to change to blacklisted file