gn analyze output:
{
  "compile_targets": [],
  "status": "Found dependency",
  "test_targets": [
    "//clang-tools-extra/test:check-clang-tools",
    "//clang/test:check-clang",
    "//compiler-rt/test/hwasan:check-hwasan",
    "//lld/test:check-lld",
    "//llvm/test:check-llvm"
  ]
}
gn analyze input:
{
  "files": [
    "//llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp",
    "//llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-align.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir",
    "//llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir",
    "//llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir",
    "//llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir",
    "//llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir",
    "//llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/copy.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fcopysign.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fneg.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir",
    "//llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/isel-sint-to-fp64-x86.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/llvm.sincos.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/regbankselect-dbg-value-physreg-crash.mir",
    "//llvm/test/CodeGen/X86/GlobalISel/regbankselect-sse-intrinsics.ll",
    "//llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll",
    "//llvm/test/CodeGen/X86/GlobalISel/sqrt.mir"
  ],
  "test_targets": [
    "//clang-tools-extra/clangd/test:check-clangd",
    "//clang-tools-extra/test:check-clang-tools",
    "//clang/test:check-clang",
    "//compiler-rt/test/hwasan:check-hwasan",
    "//lld/test:check-lld",
    "//llvm/test:check-llvm"
  ],
  "additional_compile_targets": []
}