gn analyze output:
{
  "compile_targets": [],
  "status": "Found dependency",
  "test_targets": [
    "//clang-tools-extra/clangd/test:check-clangd",
    "//clang-tools-extra/test:check-clang-tools",
    "//clang/test:check-clang",
    "//compiler-rt/test/hwasan:check-hwasan",
    "//lld/test:check-lld",
    "//llvm/test:check-llvm"
  ]
}
gn analyze input:
{
  "files": [
    "//clang/lib/AST/ByteCode/InterpBuiltin.cpp",
    "//clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp",
    "//clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp",
    "//clang/test/CIR/CodeGen/fixed-point-conversions.cpp",
    "//clang/test/CIR/CodeGen/fixed-point-literal.c",
    "//llvm/include/llvm/CodeGen/MachineBasicBlock.h",
    "//llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp",
    "//llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp",
    "//llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp",
    "//llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir",
    "//llvm/utils/profcheck-xfail.txt"
  ],
  "test_targets": [
    "//clang-tools-extra/clangd/test:check-clangd",
    "//clang-tools-extra/test:check-clang-tools",
    "//clang/test:check-clang",
    "//compiler-rt/test/hwasan:check-hwasan",
    "//lld/test:check-lld",
    "//llvm/test:check-llvm"
  ],
  "additional_compile_targets": []
}
running all tests due to change to blacklisted file