gn analyze output:
{
  "compile_targets": [],
  "status": "Found dependency",
  "test_targets": [
    "//clang-tools-extra/test:check-clang-tools",
    "//clang/test:check-clang",
    "//compiler-rt/test/hwasan:check-hwasan",
    "//lld/test:check-lld",
    "//llvm/test:check-llvm"
  ]
}
gn analyze input:
{
  "files": [
    "//llvm/lib/Target/AArch64/AArch64ISelLowering.cpp",
    "//llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp",
    "//llvm/lib/Target/AMDGPU/SIISelLowering.cpp",
    "//llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp",
    "//llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp",
    "//llvm/lib/Target/SystemZ/SystemZISelLowering.cpp",
    "//llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll",
    "//llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll",
    "//llvm/test/CodeGen/AArch64/masked-srem-scalable.ll",
    "//llvm/test/CodeGen/AArch64/masked-urem-scalable.ll",
    "//llvm/test/CodeGen/AArch64/sve-bf16-combines.ll",
    "//llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll",
    "//llvm/test/CodeGen/AArch64/sve-bitcast.ll",
    "//llvm/test/CodeGen/AArch64/sve-fpext-load.ll",
    "//llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll",
    "//llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll",
    "//llvm/test/CodeGen/AArch64/sve-lsrchain.ll",
    "//llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll",
    "//llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll",
    "//llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll",
    "//llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll",
    "//llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll",
    "//llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll",
    "//llvm/test/CodeGen/AArch64/vector-absolute-difference.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll",
    "//llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll",
    "//llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir",
    "//llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir",
    "//llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll",
    "//llvm/test/CodeGen/AMDGPU/collapse-endcf.mir",
    "//llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll",
    "//llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll",
    "//llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll",
    "//llvm/test/CodeGen/AMDGPU/loop_break.ll",
    "//llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir",
    "//llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir",
    "//llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir",
    "//llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll",
    "//llvm/test/CodeGen/AMDGPU/si-lower-control-flow-remove-redundant-block-liveintervals.mir",
    "//llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir",
    "//llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll",
    "//llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll",
    "//llvm/test/CodeGen/SystemZ/cmpxchg-01.ll",
    "//llvm/test/CodeGen/SystemZ/cmpxchg-02.ll",
    "//llvm/test/CodeGen/SystemZ/dead-cc-defs.ll",
    "//llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll",
    "//mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h",
    "//mlir/lib/Dialect/Vector/Transforms/VectorMaskElimination.cpp",
    "//mlir/test/Dialect/Vector/eliminate-masks.mlir",
    "//mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp"
  ],
  "test_targets": [
    "//clang-tools-extra/clangd/test:check-clangd",
    "//clang-tools-extra/test:check-clang-tools",
    "//clang/test:check-clang",
    "//compiler-rt/test/hwasan:check-hwasan",
    "//lld/test:check-lld",
    "//llvm/test:check-llvm"
  ],
  "additional_compile_targets": []
}