gn analyze output: { "compile_targets": [], "status": "Found dependency", "test_targets": [ "//clang-tools-extra/clangd/test:check-clangd", "//clang-tools-extra/test:check-clang-tools", "//clang/test:check-clang", "//lld/test:check-lld", "//llvm/test:check-llvm" ] } gn analyze input: { "files": [ "//libcxxabi/src/cxa_default_handlers.cpp", "//llvm/include/llvm/CodeGen/MachineScheduler.h", "//llvm/include/llvm/InitializePasses.h", "//llvm/include/llvm/Passes/CodeGenPassBuilder.h", "//llvm/include/llvm/Passes/MachinePassRegistry.def", "//llvm/lib/CodeGen/CodeGen.cpp", "//llvm/lib/CodeGen/MachineScheduler.cpp", "//llvm/lib/CodeGen/RegAllocBasic.cpp", "//llvm/lib/CodeGen/RegAllocGreedy.cpp", "//llvm/lib/Passes/PassBuilder.cpp", "//llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp", "//llvm/test/CodeGen/AArch64/a55-fuse-address.mir", "//llvm/test/CodeGen/AArch64/ampere1-sched-add.mir", "//llvm/test/CodeGen/AArch64/cluster-frame-index.mir", "//llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir", "//llvm/test/CodeGen/AArch64/dump-schedule-trace.mir", "//llvm/test/CodeGen/AArch64/force-enable-intervals.mir", "//llvm/test/CodeGen/AArch64/machine-scheduler.mir", "//llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir", "//llvm/test/CodeGen/AArch64/macro-fusion-last.mir", "//llvm/test/CodeGen/AArch64/misched-branch-targets.mir", "//llvm/test/CodeGen/AArch64/misched-bundle.mir", "//llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir", "//llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir", "//llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir", "//llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir", "//llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir", "//llvm/test/CodeGen/AArch64/misched-move-imm.mir", "//llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir", "//llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir", "//llvm/test/CodeGen/AArch64/sched-postidxalias.mir", "//llvm/test/CodeGen/AArch64/sched-print-cycle.mir", "//llvm/test/CodeGen/AArch64/scheduledag-constreg.mir", "//llvm/test/CodeGen/AArch64/sve-aliasing.mir", "//llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir", "//llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir", "//llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir", "//llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir", "//llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir", "//llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir", "//llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir", "//llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir", "//llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir", "//llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir", "//llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir", "//llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir", "//llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir", "//llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir", "//llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir", "//llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir", "//llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir", "//llvm/test/CodeGen/AMDGPU/schedule-barrier.mir", "//llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir", "//llvm/test/CodeGen/ARM/cortex-m7-wideops.mir", "//llvm/test/CodeGen/ARM/misched-branch-targets.mir", "//llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir", "//llvm/test/CodeGen/RISCV/misched-postra-direction.mir", "//utils/bazel/llvm-project-overlay/mlir/BUILD.bazel" ], "test_targets": [ "//clang-tools-extra/clangd/test:check-clangd", "//clang-tools-extra/test:check-clang-tools", "//clang/test:check-clang", "//lld/test:check-lld", "//llvm/test:check-llvm" ], "additional_compile_targets": [] } running all tests due to change to blacklisted file