gn analyze output:
{
  "compile_targets": [],
  "status": "Found dependency",
  "test_targets": [
    "//clang-tools-extra/clangd/test:check-clangd",
    "//clang-tools-extra/test:check-clang-tools",
    "//clang/test:check-clang",
    "//lld/test:check-lld",
    "//llvm/test:check-llvm"
  ]
}
gn analyze input:
{
  "files": [
    "//llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h",
    "//llvm/lib/Target/RISCV/RISCVProcessors.td",
    "//llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp",
    "//llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp",
    "//llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/stacksave-stackrestore.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll",
    "//llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll",
    "//llvm/test/CodeGen/RISCV/abds-neg.ll",
    "//llvm/test/CodeGen/RISCV/abds.ll",
    "//llvm/test/CodeGen/RISCV/abdu-neg.ll",
    "//llvm/test/CodeGen/RISCV/abdu.ll",
    "//llvm/test/CodeGen/RISCV/add-before-shl.ll",
    "//llvm/test/CodeGen/RISCV/add-imm.ll",
    "//llvm/test/CodeGen/RISCV/alloca.ll",
    "//llvm/test/CodeGen/RISCV/alu64.ll",
    "//llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll",
    "//llvm/test/CodeGen/RISCV/atomic-rmw.ll",
    "//llvm/test/CodeGen/RISCV/atomic-signext.ll",
    "//llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll",
    "//llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll",
    "//llvm/test/CodeGen/RISCV/bf16-promote.ll",
    "//llvm/test/CodeGen/RISCV/bfloat-convert.ll",
    "//llvm/test/CodeGen/RISCV/bfloat-mem.ll",
    "//llvm/test/CodeGen/RISCV/bfloat.ll",
    "//llvm/test/CodeGen/RISCV/bittest.ll",
    "//llvm/test/CodeGen/RISCV/branch-on-zero.ll",
    "//llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll",
    "//llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll",
    "//llvm/test/CodeGen/RISCV/callee-saved-gprs.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-half.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-lp64.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll",
    "//llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll",
    "//llvm/test/CodeGen/RISCV/calls.ll",
    "//llvm/test/CodeGen/RISCV/codemodel-lowering.ll",
    "//llvm/test/CodeGen/RISCV/condbinops.ll",
    "//llvm/test/CodeGen/RISCV/condops.ll",
    "//llvm/test/CodeGen/RISCV/copysign-casts.ll",
    "//llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll",
    "//llvm/test/CodeGen/RISCV/double-calling-conv.ll",
    "//llvm/test/CodeGen/RISCV/double-convert.ll",
    "//llvm/test/CodeGen/RISCV/double-fcmp-strict.ll",
    "//llvm/test/CodeGen/RISCV/double-imm.ll",
    "//llvm/test/CodeGen/RISCV/double-mem.ll",
    "//llvm/test/CodeGen/RISCV/double-round-conv-sat.ll",
    "//llvm/test/CodeGen/RISCV/double-select-fcmp.ll",
    "//llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll",
    "//llvm/test/CodeGen/RISCV/fastcc-bf16.ll",
    "//llvm/test/CodeGen/RISCV/fastcc-float.ll",
    "//llvm/test/CodeGen/RISCV/fastcc-half.ll",
    "//llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll",
    "//llvm/test/CodeGen/RISCV/float-convert.ll",
    "//llvm/test/CodeGen/RISCV/float-fcmp-strict.ll",
    "//llvm/test/CodeGen/RISCV/float-select-fcmp.ll",
    "//llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll",
    "//llvm/test/CodeGen/RISCV/forced-atomics.ll",
    "//llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll",
    "//llvm/test/CodeGen/RISCV/fp128.ll",
    "//llvm/test/CodeGen/RISCV/fpclamptosat.ll",
    "//llvm/test/CodeGen/RISCV/get-setcc-result-type.ll",
    "//llvm/test/CodeGen/RISCV/half-arith.ll",
    "//llvm/test/CodeGen/RISCV/half-convert-strict.ll",
    "//llvm/test/CodeGen/RISCV/half-convert.ll",
    "//llvm/test/CodeGen/RISCV/half-fcmp-strict.ll",
    "//llvm/test/CodeGen/RISCV/half-intrinsics.ll",
    "//llvm/test/CodeGen/RISCV/half-mem.ll",
    "//llvm/test/CodeGen/RISCV/half-select-fcmp.ll",
    "//llvm/test/CodeGen/RISCV/iabs.ll",
    "//llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll",
    "//llvm/test/CodeGen/RISCV/inline-asm-d-modifier-N.ll",
    "//llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll",
    "//llvm/test/CodeGen/RISCV/inline-asm-f-modifier-N.ll",
    "//llvm/test/CodeGen/RISCV/inline-asm-zfinx-constraint-r.ll",
    "//llvm/test/CodeGen/RISCV/inline-asm-zhinx-constraint-r.ll",
    "//llvm/test/CodeGen/RISCV/inline-asm.ll",
    "//llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll",
    "//llvm/test/CodeGen/RISCV/legalize-fneg.ll",
    "//llvm/test/CodeGen/RISCV/llvm.exp10.ll",
    "//llvm/test/CodeGen/RISCV/llvm.frexp.ll",
    "//llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll",
    "//llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll",
    "//llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll",
    "//llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll",
    "//llvm/test/CodeGen/RISCV/mem.ll",
    "//llvm/test/CodeGen/RISCV/mem64.ll",
    "//llvm/test/CodeGen/RISCV/memcmp-optsize.ll",
    "//llvm/test/CodeGen/RISCV/memcmp.ll",
    "//llvm/test/CodeGen/RISCV/memmove.ll",
    "//llvm/test/CodeGen/RISCV/memset-pattern.ll",
    "//llvm/test/CodeGen/RISCV/mul.ll",
    "//llvm/test/CodeGen/RISCV/neg-abs.ll",
    "//llvm/test/CodeGen/RISCV/orc-b-patterns.ll",
    "//llvm/test/CodeGen/RISCV/overflow-intrinsics.ll",
    "//llvm/test/CodeGen/RISCV/pr51206.ll",
    "//llvm/test/CodeGen/RISCV/pr58511.ll",
    "//llvm/test/CodeGen/RISCV/pr63816.ll",
    "//llvm/test/CodeGen/RISCV/pr69586.ll",
    "//llvm/test/CodeGen/RISCV/push-pop-popret.ll",
    "//llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll",
    "//llvm/test/CodeGen/RISCV/rotl-rotr.ll",
    "//llvm/test/CodeGen/RISCV/rv32-inline-asm-pairs.ll",
    "//llvm/test/CodeGen/RISCV/rv32zbb.ll",
    "//llvm/test/CodeGen/RISCV/rv32zbs.ll",
    "//llvm/test/CodeGen/RISCV/rv64-double-convert.ll",
    "//llvm/test/CodeGen/RISCV/rv64-half-convert.ll",
    "//llvm/test/CodeGen/RISCV/rv64-inline-asm-pairs.ll",
    "//llvm/test/CodeGen/RISCV/rv64-trampoline.ll",
    "//llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll",
    "//llvm/test/CodeGen/RISCV/rv64zbkb.ll",
    "//llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll",
    "//llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll",
    "//llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll",
    "//llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll",
    "//llvm/test/CodeGen/RISCV/rvv/calling-conv.ll",
    "//llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll",
    "//llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll",
    "//llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll",
    "//llvm/test/CodeGen/RISCV/rvv/copyprop.mir",
    "//llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll",
    "//llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll",
    "//llvm/test/CodeGen/RISCV/rvv/expandload.ll",
    "//llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll",
    "//llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll",
    "//llvm/test/CodeGen/RISCV/rvv/floor-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll",
    "//llvm/test/CodeGen/RISCV/rvv/frm-insert.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll",
    "//llvm/test/CodeGen/RISCV/rvv/localvar.ll",
    "//llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll",
    "//llvm/test/CodeGen/RISCV/rvv/memory-args.ll",
    "//llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll",
    "//llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll",
    "//llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll",
    "//llvm/test/CodeGen/RISCV/rvv/pr125306.ll",
    "//llvm/test/CodeGen/RISCV/rvv/pr63596.ll",
    "//llvm/test/CodeGen/RISCV/rvv/pr95865.ll",
    "//llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/round-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll",
    "//llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll",
    "//llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll",
    "//llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll",
    "//llvm/test/CodeGen/RISCV/rvv/stepvector.ll",
    "//llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll",
    "//llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll",
    "//llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmseq.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmsge.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmsgt.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmsle.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmsleu.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmslt.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmsltu.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmsne.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vpload.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vpstore.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll",
    "//llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll",
    "//llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll",
    "//llvm/test/CodeGen/RISCV/scmp.ll",
    "//llvm/test/CodeGen/RISCV/select-and.ll",
    "//llvm/test/CodeGen/RISCV/select-bare.ll",
    "//llvm/test/CodeGen/RISCV/select-cc.ll",
    "//llvm/test/CodeGen/RISCV/select-constant-xor.ll",
    "//llvm/test/CodeGen/RISCV/select-optimize-multiple.ll",
    "//llvm/test/CodeGen/RISCV/select-or.ll",
    "//llvm/test/CodeGen/RISCV/sextw-removal.ll",
    "//llvm/test/CodeGen/RISCV/shift-amount-mod.ll",
    "//llvm/test/CodeGen/RISCV/shifts.ll",
    "//llvm/test/CodeGen/RISCV/shl-cttz.ll",
    "//llvm/test/CodeGen/RISCV/split-offsets.ll",
    "//llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll",
    "//llvm/test/CodeGen/RISCV/srem-vector-lkk.ll",
    "//llvm/test/CodeGen/RISCV/stack-slot-size.ll",
    "//llvm/test/CodeGen/RISCV/stack-store-check.ll",
    "//llvm/test/CodeGen/RISCV/tail-calls.ll",
    "//llvm/test/CodeGen/RISCV/ucmp.ll",
    "//llvm/test/CodeGen/RISCV/unaligned-load-store.ll",
    "//llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll",
    "//llvm/test/CodeGen/RISCV/urem-vector-lkk.ll",
    "//llvm/test/CodeGen/RISCV/vararg.ll",
    "//llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll",
    "//llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll",
    "//llvm/test/CodeGen/RISCV/xaluo.ll",
    "//llvm/test/CodeGen/RISCV/xtheadmemidx.ll",
    "//llvm/test/CodeGen/RISCV/xtheadmempair.ll",
    "//llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll",
    "//llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll",
    "//llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll",
    "//llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll",
    "//llvm/unittests/Transforms/Vectorize/SandboxVectorizer/InstrMapsTest.cpp"
  ],
  "test_targets": [
    "//clang-tools-extra/clangd/test:check-clangd",
    "//clang-tools-extra/test:check-clang-tools",
    "//clang/test:check-clang",
    "//lld/test:check-lld",
    "//llvm/test:check-llvm"
  ],
  "additional_compile_targets": []
}
running all tests due to change to blacklisted file