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[76/1990] ACTION //llvm/lib/Target/RISCV/MCTargetDesc:RISCVGenInstrInfo(//llvm/utils/gn/build/toolchain:unix)
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[152/1939] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyTargetMachine.o
[153/1939] AR lib/libLLVMWebAssemblyCodeGen.a
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[157/1939] AR lib/libLLVMExegesisPowerPC.a
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[161/1939] ACTION //llvm/lib/Target/RISCV:RISCVGenMacroFusion(//llvm/utils/gn/build/toolchain:unix)
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[166/1939] AR lib/libLLVMNVPTXCodeGen.a
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[172/1935] ACTION //llvm/lib/Target/RISCV:RISCVGenGlobalISel(//llvm/utils/gn/build/toolchain:unix)
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[175/1933] CXX obj/llvm/lib/Target/PowerPC/GISel/LLVMPowerPCCodeGen.PPCCallLowering.o
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[177/1933] CXX obj/llvm/tools/llvm-exegesis/lib/lib.ResultAggregator.o
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[185/1933] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86ISelLowering.o
[186/1933] CXX obj/llvm/tools/llvm-exegesis/lib/lib.SubprocessMemory.o
[187/1933] AR lib/libLLVMX86CodeGen.a
[188/1933] AR lib/libLLVMSystemZCodeGen.a
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[193/1933] CXX obj/llvm/tools/llvm-exegesis/lib/lib.Target.o
[194/1933] CXX obj/llvm/tools/llvm-exegesis/lib/RISCV/RISCV.RISCVExegesisPreprocessing.o
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[199/1933] AR lib/libLLVMExegesisRISCV.a
[200/1933] AR lib/libLLVMExegesis.a
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[204/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVAsmPrinter.o
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[220/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVLateBranchOpt.o
[221/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVLoadStoreOptimizer.o
[222/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVInterleavedAccess.o
[223/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVInstrInfo.o
[224/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVMachineFunctionInfo.o
[225/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVMakeCompressible.o
[226/1933] CXX obj/llvm/lib/Target/RISCV/GISel/LLVMRISCVCodeGen.RISCVInstructionSelector.o
[227/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVMoveMerger.o
[228/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVMergeBaseOffset.o
[229/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVPushPopOptimizer.o
[230/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVISelDAGToDAG.o
[231/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVOptWInstrs.o
[232/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVSelectionDAGInfo.o
[233/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVRegisterInfo.o
[234/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVSubtarget.o
[235/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVTargetObjectFile.o
[236/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVISelLowering.o
[237/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVVMV0Elimination.o
[238/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVVectorMaskDAGMutation.o
[239/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVVLOptimizer.o
[240/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVVectorPeephole.o
[241/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVZacasABIFix.o
[242/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVTargetMachine.o
[243/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCBranchCoalescing.o
[244/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCCTRLoopsVerify.o
[245/1933] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVTargetTransformInfo.o
[246/1933] AR lib/libLLVMRISCVCodeGen.a
[247/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCBoolRetToInt.o
[248/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCEarlyReturn.o
[249/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCBranchSelector.o
[250/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCCTRLoops.o
[251/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCExpandAtomicPseudoInsts.o
[252/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCAsmPrinter.o
[253/1933] CXX obj/llvm/lib/Target/PowerPC/GISel/LLVMPowerPCCodeGen.PPCInstructionSelector.o
[254/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCCallingConv.o
[255/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCGenScalarMASSEntries.o
[256/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCHazardRecognizers.o
[257/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCFastISel.o
[258/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCFrameLowering.o
[259/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCLowerMASSVEntries.o
[260/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCMCInstLower.o
[261/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCMachineScheduler.o
[262/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCInstrInfo.o
[263/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCLoopInstrFormPrep.o
[264/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCMacroFusion.o
[265/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCISelDAGToDAG.o
[266/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCSelectionDAGInfo.o
[267/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCMIPeephole.o
[268/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCPreEmitPeephole.o
[269/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCReduceCRLogicals.o
[270/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCRegisterInfo.o
[271/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCTOCRegDeps.o
[272/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCSubtarget.o
[273/1933] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCTLSDynamicCall.o
[274/1933] ACTION //llvm/lib/Target/LoongArch/MCTargetDesc:LoongArchGenAsmWriter(//llvm/utils/gn/build/toolchain:unix)
[275/1933] ACTION //llvm/lib/Target/LoongArch/MCTargetDesc:LoongArchGenMCCodeEmitter(//llvm/utils/gn/build/toolchain:unix)
[276/1933] ACTION //llvm/lib/Target/LoongArch/MCTargetDesc:LoongArchGenInstrInfo(//llvm/utils/gn/build/toolchain:unix)
[277/1906] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCVSXWACCCopy.o
[278/1906] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCISelLowering.o
[279/1906] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCVSXFMAMutate.o
[280/1906] ACTION //llvm/lib/Target/Mips/Disassembler:MipsGenDisassemblerTables(//llvm/utils/gn/build/toolchain:unix)
FAILED: gen/llvm/lib/Target/Mips/Disassembler/MipsGenDisassemblerTables.inc 
python3 ../../llvm/utils/gn/build/run_built_binary.py bin/llvm-tblgen --write-if-changed -I ../../llvm/include -I ../../llvm/lib/Target/Mips -d gen/llvm/lib/Target/Mips/Disassembler/MipsGenDisassemblerTables.inc.d -o gen/llvm/lib/Target/Mips/Disassembler/MipsGenDisassemblerTables.inc ../../llvm/lib/Target/Mips/Mips.td -gen-disassembler
Included from ../../llvm/lib/Target/Mips/Mips.td:221:
Included from ../../llvm/lib/Target/Mips/MipsInstrInfo.td:3388:
../../llvm/lib/Target/Mips/Mips16InstrInfo.td:778:5: error: could not find field for operand 'rs'
def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIM16Alu> {
    ^
Included from ../../llvm/lib/Target/Mips/Mips.td:221:
Included from ../../llvm/lib/Target/Mips/MipsInstrInfo.td:3388:
../../llvm/lib/Target/Mips/Mips16InstrInfo.td:857:5: error: could not find field for operand 'size'
def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
    ^
Included from ../../llvm/lib/Target/Mips/Mips.td:221:
Included from ../../llvm/lib/Target/Mips/MipsInstrInfo.td:3388:
../../llvm/lib/Target/Mips/Mips16InstrInfo.td:859:5: error: could not find field for operand 'size'
def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
    ^
Included from ../../llvm/lib/Target/Mips/Mips.td:221:
Included from ../../llvm/lib/Target/Mips/MipsInstrInfo.td:3408:
../../llvm/lib/Target/Mips/MicroMipsInstrInfo.td:1132:7: error: could not find field for operand 'sel'
  def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
      ^
Assertion failed: (!OpInfo.Decoder.empty()), function emitBinaryParser, file DecoderEmitter.cpp, line 1129.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.	Program arguments: ./bin/llvm-tblgen --write-if-changed -I ../../llvm/include -I ../../llvm/lib/Target/Mips -d gen/llvm/lib/Target/Mips/Disassembler/MipsGenDisassemblerTables.inc.d -o gen/llvm/lib/Target/Mips/Disassembler/MipsGenDisassemblerTables.inc ../../llvm/lib/Target/Mips/Mips.td -gen-disassembler
[281/1906] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCVSXSwapRemoval.o
[282/1906] ACTION //llvm/lib/Target/Hexagon/MCTargetDesc:HexagonGenAsmWriter(//llvm/utils/gn/build/toolchain:unix)
[283/1904] CXX obj/llvm/lib/Target/PowerPC/AsmParser/AsmParser.PPCAsmParser.o
[284/1904] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCTargetMachine.o
[285/1904] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsModuleISelDAGToDAG.o
[286/1904] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCTargetTransformInfo.o
[287/1904] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsOptimizePICCall.o
[288/1904] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsISelDAGToDAG.o
[289/1904] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsPostLegalizerCombiner.o
ninja: build stopped: subcommand failed.
Command '['ninja', '-C', 'out/gn']' returned non-zero exit status 1.